Information processing devices including image processors for consumer use generally use large-capacity and low-cost DRAMs to store a large amount of data. In particular, recent image processors require DRAMs with not just memory capacity but with high data transferring capability for High Definition (HD) image processing in MPEG 2, H.264, or the like, simultaneous multiple channel processing, and high-quality 3-D graphics processing. In order to achieve the high data transferring capability, some conventional methods are known including: (1) increasing the operating frequency of bus; (2) allowing a wide bus width in a memory; and a method with the combination of (1) and (2).
When accessing a DRAM, it is necessary to activate a bank and a row to be accessed for designating the bank and the row in advance. In addition, when changing a row to be accessed in the same bank, it is necessary to precharge the accessed row first, and activate the row to be newly accessed. During the activation process and the precharge process, the bank cannot be accessed, which generates an inaccessible period when switching the row in the same bank and generates idle cycle in data bus. In order to compensate for the disadvantage, in a regular DRAM access control, a control referred to as bank interleaving is performed. The bank interleaving masks the inaccessible period by activating and precharging another bank while transferring data to a certain bank, thereby allowing constant data transfer with the DRAM on the data bus. For effective bank interleaving, it is required to have longer continuous data transfer time to a same bank so as to mask the inaccessible period of a bank by transferring data to another bank.
Patent Literature 1 discloses a conventional method to solve the problem of the inefficient transfer due to the inaccessible period. In this method, time-division accesses are carried out alternately to memories A and B at a predetermined timing based on signals from counters 0 and 1 so that the inaccessible period generated in one of the memories is masked by the data transfer time of the other memory. In such a manner, bus access efficiency is improved. However, with the conventional technique, although multiple memories are used, only one memory is accessible at one time; and thus, the maximum memory bandwidth that can be used in a system is limited to the memory bandwidth of one memory.
FIG. 1A is a diagram showing various types of DRAMs, operating frequencies, and burst length according to the conventional technique. FIG. 1A shows four types of DRAMs: Single Data Rate (SDR) Synchronous DRAM (SDRAM); Double Data Rate (DDR) SDRAM; DDR2 SDRAM; and DDR3 SDRAM (hereinafter, referred to as SDR, DDR, DDR2, and DDR3). FIG. 1A shows the operating frequency of the internal bus and the operating frequency of the data bus for each of the four types of DRAMs. The data bus includes a bus width of multiple bits such as 32 bits or 64 bits; however, for ease of description, FIG. 1A shows only a portion corresponding to 1 bit.
The SDR includes a memory core and an I/O buffer. The memory core corresponds to one memory cell array, and inputs and outputs, to and from the data bus via the I/O buffer, 1-bit data of the memory cell array designated by a row address and a column address. The operating frequency of the internal bus of the SDR (133 MHz) is the same as the operating frequency of the external data bus (133 MHz).
The respective memory cores of the DDR, DDR2, and DDR3 are almost same as the memory core of the SDR.
The upper limit of the operating frequency of the internal bus is determined by the upper limit of the operating frequency of the memory core. More specifically, it is considered that the upper limit of the frequency to which capacitors used as memory cells can respond is approximately 200 MHz, and thus, the operating frequency of the memory core cannot exceed approximately 200 MHz, either. On the other hand, a master which accesses memories is becoming faster and faster every year. In the DDR, DDR2 and DDR3, for speeding up the DRAM, a method is used where multiple bit data are input and output in parallel between the I/O buffer and the memory core, and the data are serially input and output between the I/O buffer and the data bus.
The I/O buffer of the DDR inputs and outputs 2-bit data in parallel to and from the memory core at the operating frequency of 133 MHz, and serially inputs and outputs the data to and from the data bus at the operating frequency of 266 MHz which is double the operating frequency of the internal bus. The minimum burst length (referred to also as a base burst length) in the DDR is 2.
The I/O buffer of the DDR2 inputs and outputs 4-bit data in parallel to and from the memory core at the operating frequency of 133 MHz, and inputs and outputs the data serially to and from the data bus at the operating frequency of 533 MHz which is substantially four times the operating frequency of the internal bus. The minimum burst length in the DDR2 is 4.
The I/O buffer of the DDR3 inputs and outputs 8-bit data in parallel to and from the memory core at the operating frequency of 133 MHz, and inputs and outputs the data serially to and from the data bus at the operating frequency of 1066 MHz which is substantially eight times the operating frequency of the internal bus. The minimum burst length in the DDR3 is 8. In order to maintain compatibility with DDR2, the DDR3 has a function to support the burst length of 4 by destroying last 4 bits out of 8 bits held in the I/O buffer (burst chop function).
As described, the SDRAM increases the operating frequency of the external data bus, that is, increases memory bandwidth, by increasing the number of bits of the I/O buffer. In such a manner, the SDRAM compensates for the difficulty of increasing the operating frequency of the internal bus.
FIG. 1B is a diagram showing an example of a data arrangement for effective bank interleaving in a general DRAM. The data is arrangement includes data in a first bank, which are continuous with the same row address and has N bytes represented by “base burst length×bus width” (hereinafter, referred to as a base access unit), followed by data of the base access unit in a second bank. The examples of the base burst length are 1 for SDRAM, 2 for DDR, 4 for DDR2, and 8 for DDR3. Subsequently, continuous data with the same row address in a M-th bank is arranged in the similar manner. This allows efficient bank interleaving because multiple banks appear evenly at the time of memory access. FIG. 1B shows an example where two banks are included. In a general DRAM, it is not possible to transfer data less than the base burst length (data of “base burst length×bus width” is always input or output upon one access request); and thus, the base access unit is the same as the minimum access unit.
FIG. 2 shows an example where access to unnecessary data occurs in the data sequence arranged as in FIG. 1B. In the case where the data area of the requested access (hereinafter, referred to as an access requested area) is N bytes starting from the middle of the base access unit as shown in FIG. 2, a data request is required for all base access units including the access requested area, because the minimum access unit is, the same as the base access unit. As a result, it is necessary to access to 2N bytes (hereinafter, referred to as an access required area) as shown in FIG. 2. Although the access required area is 2N bytes, the access requested area is only N byte. The data of N-byte that is the difference between the two results in unnecessary data, which leads to a decrease in data transfer efficiency.